The present invention relates generally to detecting the updating of recovery unit (R-unit) registers and in particular to a write-before-read interlock that returns data as soon as it is available. A detailed description of a recovery unit for mirrored processors is found in U.S. Pat. No. 5,692,121 to Bozso et al., issued Nov. 25, 1997, and incorporated by reference.
Currently, high performance processors are typically pipelined. Pipelining is a method of processing that allows for fast concurrent processing of data. This is accomplished by overlapping operations in a portion of memory that passes information from one process to another process. Most processor instructions have to go through the same basic sequence: the instruction must be fetched, it must be decoded, it must have its operands fetched, (which may first require-address generation), it must be executed, and its results must be put away. The pipelining method fetches and decodes instructions in which, at any given time, several program instructions are in various stages of being fetched or decoded. The pipelining method improves the speed of system execution time by ensuring that the microprocessor does not have to wait for instructions. When the processor completes execution of one instruction, the next instruction is ready to be performed.
Computer systems contain several types of registers including General Purpose registers (GPRs), Access registers (ARs), Floating Point registers (FPRs), Host and Guest Control registers (CRs). The millicode architecture contains additional registers —Millicode General Purpose registers (MGRs), Millicode Access registers (MARs), Millicode Control registers (MCRs), and System registers (SYSRs). These millicode registers may only be directly accessed by millicode instructions. There are multiple copies of some of these registers throughout the processor, for performance and cycle-time reasons. When an instruction is executed which updates one of these registers, the new value is placed on a common bus “C-bus” during the put-away stage of the pipeline, and all copies of the registers are updated from the common bus. In order to be able to recover from errors, one copy of every register is contained in the R-unit, and protected by an Error Correction Code (ECC). All the registers in the R-unit are assigned an 8-bit address. In order to recover from errors, all of these registers, and storage, must be “check-pointed”. This means that at any given time, there must be one copy of the registers and storage that reflect the results at the completion of an instruction. In other words, if an instruction updates multiple registers, or a register and storage, either all of the updates must be visible, or none of them. When an error is encountered, all copies of the registers are restored to their check-pointed state, and return control back to the point following the last instruction to complete. The R-unit copy of the registers is the check-pointed copy. Ensuring that the register updates are synchronous with any storage updates requires additional machine cycles from when the results are “put-away” until they are check-pointed. GPRs, ARs, FPRs, MGRs, and MARs are used frequently, so they must be accessible without incurring any stalls in the pipeline, or performance would suffer. Thus, the execution unit contains copies of these registers so that they may be accessed locally without incurring a pipeline stall. CRs and MCRs are not used frequently, so performance is not significantly impacted if a pipeline stall is encountered while accessing them. Thus, the only copy of these registers is the ECC protected copy in the R-unit. Because of the additional cycles after the put-away cycle required to maintain the R-unit checkpoint, access to registers from the R-unit may incur pipeline stalls.
Typically, these R-unit operands are not used or updated until late in the pipeline. This results in the loss of processor time due to unnecessary clock cycles. In addition, instructions in the pipeline may update an R-unit register that is a source operand used in a later instruction (pre-fetching) for its operands. Again, this condition is not efficient and results in added clock cycles. Consequently, there is a need for a quicker and more efficient method of detecting when R-unit registers are being updated during the pre-fetching of operands period to guarantee that the correct values are sent for access to register operands in the R-unit with a minimum number of clock cycles required.